WORD LINE DISABLE SIGNAL GENERATION CIRCUIT OF SUB-WORD LINE DRIVER

摘要

PURPOSE: A word line disable signal generation circuit of a sub-word line driver is provided to reduce the precharge time of low address signal during the word line disable by controlling the period between the sub-word line driving signal and the normal word line enable signal to have a predetermined delay time. CONSTITUTION: A word line disable signal generation circuit of a sub-word line driver includes a first NAND gate(ND1), a second NAND gate(ND2), a second inverter(IN2), a latch block(30) and a third inverter(IN3). The first NAND gate(ND1) inputs the decoded row address signal 1 outputted from the first inverter(IN1) and a signal delayed through the delay block. The second NAND gate(ND2) inputs the decoded row address signal 2 and the decoded row address signal 3. The second inverter(IN2) inverts the signal outputted from the second NAND gate(ND2). The latch block(30) receives the signal outputted from the second inverter(IN2) and the signal outputted from the first NAND gate(ND1). And, the third inverter(IN3) inverts the signal outputted from the latch block(30).