METHOD OF FABRICATING COMPLEMENTARY MOS TRANSISTOR FOR REMOVING LATCH-UP PHENOMENON

摘要

PURPOSE: A method of fabricating a complementary MOS transistor is provided to form stably a channel region and improve a latch-up channel characteristic by forming a polysilicon layer having a thickness of 5000 angstrom. CONSTITUTION: An insulating layer and a polysilicon layer are formed on a semiconductor substrate. A P-well region and an N-well region are formed by implanting different conductive type impurities into the polysilicon layer. A trench-etching process is performed by using a photoresist layer pattern for exposing an interface between the P-well and the N-well. Boron ions are implanted therein. An insulating layer is deposited thereon. The trench-etching process is performed from by using the photoresist layer pattern for exposing a transistor region. A gate oxide layer is formed thereon. A gate electrode(75) is formed on thereon.