发明名称 CAPACITOR-INCORPORATED SUBSTRATE AND CHIP TYPE CAPACITOR
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a capacitor-incorporated substrate and a chip type capacitor which improve the strength and flatness of a laminated body by deterring shrinkage in surface direction. <P>SOLUTION: The laminated body 1 is formed by alternately laminating 1st dielectric layers 1a to 1f and 2nd dielectric layers 1g to 1l formed by burning two kinds of compositionally different inorganic constituents. 1st electrode layers 2a and 2nd electrode layers 2b are alternately interposed between the 1st dielectric layers and 2nd dielectric layers which are adjacent along the thickness of the laminated body 1 while partially facing each other, and also electrically connected to a conductor layer 4 bonded to the external surface of the laminated body 1. Further, the 2nd dielectric layers 1g to 1l are thicker than the 1st dielectric layers 1a to 1f and burnt at a temperature higher than that for the 1st dielectric layers. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p>
申请公布号 JP2004235374(A) 申请公布日期 2004.08.19
申请号 JP20030021206 申请日期 2003.01.29
申请人 KYOCERA CORP 发明人 SAITO TOSHIYUKI
分类号 H01G4/12;H01G4/30;H05K3/46;(IPC1-7):H01G4/12 主分类号 H01G4/12
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