| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a data buffer device capable of preventing a spike from occurring in a write enabling signal and a read enabling signal in the case of using an asynchronous clock signal to write and read data. <P>SOLUTION: The permission/nonpermission of write and read to/from data storage devices 1_0 to 1_7 is controlled in accordance with the states of a lock signal L[i] and an unlock signal U[i]. The lock signal L[i] and the unlock signal U[i] are transmitted over circuit blocks that operate with different clock signals (CK1 and CK2), and are are converted into signals (synchronized lock signal LS[i] and synchronized unlock signal US[i]) which do not include an abnormal signal in a metastable state and are synchronized with the other clock signal by going through a synchronizing circuits 3 and 5 when the signals are inputted to the other clock system. <P>COPYRIGHT: (C)2004,JPO&NCIPI</p> |
