发明名称 SYSTEM CLOCK CONTROLLER AND CONTROL METHOD OF STREAM RECEIVER
摘要 <P>PROBLEM TO BE SOLVED: To obtain an appropriate system clock even when PCR (Program Clock Reference) and SCR (System Clock Reference) are unsuitable as a reference signal for generating a system clock. <P>SOLUTION: When a stream is decoded, an STD buffer control section 144 detects the effective volume of data of a buffer for temporarily storing that stream, a function generating section 145 generates a specified function based on the detected volume of data, and the oscillation frequency of a VCO 141 in a PLL generating a system clock being employed at the time of decoding a data stream is controlled. A system clock having an appropriate frequency is thereby attained and overflow and underflow of the STD buffer are prevented. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2004328423(A) 申请公布日期 2004.11.18
申请号 JP20030121035 申请日期 2003.04.25
申请人 TOSHIBA CORP 发明人 NAKANO HIROYUKI;SAKAMOTO NORIYA
分类号 H04L7/033;H04N7/24;H04N19/00;H04N19/102;H04N19/152;H04N19/196;H04N19/44;H04N19/70 主分类号 H04L7/033
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