| 发明名称 |
ON-CHIP TEST CIRCUIT FOR MAGNETIC RANDOM ACCESS MEMORY (MRAM) |
| 摘要 |
Embodiments include a test circuit to test one or more magnetic tunnel junctions (MTJs) of a magnetic random access memory (MRAM). The test circuit may measure a 1/f noise of the MTJ in the time domain, and determine a power spectral density (PSD) of the 1/f noise. The test circuit may estimate one or more parameters of the MTJ and/or MRAM based on the PSD. For example, the test circuit may determine a noise parameter, such as a Hooge alpha parameter, based on the PSD, and may estimate the one or more parameters of the MTJ and/or MRAM based on the 1/f parameter. Other embodiments may be described and claimed. |
| 申请公布号 |
US2016377669(A1) |
申请公布日期 |
2016.12.29 |
| 申请号 |
US201514749324 |
申请日期 |
2015.06.24 |
| 申请人 |
Manipatruni Sasikanth;Lin Chia-Ching;Wang Yih;Young Ian A. |
发明人 |
Manipatruni Sasikanth;Lin Chia-Ching;Wang Yih;Young Ian A. |
| 分类号 |
G01R31/12;G11C29/00;G01R29/26;G11C11/16 |
主分类号 |
G01R31/12 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A circuit comprising:
a magnetic random access memory (MRAM) including an MRAM cell that includes a magnetic tunnel junction (MTJ); and a test circuit, coupled to the MRAM, to:
measure a noise of the MTJ in a time domain; andestimate a breakdown voltage of the MTJ based on the measured noise. |
| 地址 |
Hillsboro OR US |
