| 摘要 |
<p>Two programmable pairs of memories contain sample words of a reference signal and which were precalculated on a computer. One memory contains samples for odd steps while the other contains the even steps. These memories receive the same address during two successive sampling periods via two busses and are controlled for the read periods by complementary logic signals from a time base generator. Addressing of the memory cells is processed by an address counter containing three four bit sub counters. These are initialised by a synchronising signal from a clock running at the line frequency. The memory output passes via a unity adder or subtractor controlled from the time base. A digital-analogue is controlled to provide the amplitude required of the waveform.</p> |
