| 摘要 |
PURPOSE:To prevent the delay of the processing of a processor based upon the response delay of a bus control circuit, by providing a bus control circuit for avoiding the contention of the use of a single common bus. CONSTITUTION:When a bus request signal BSRQc arrives from a processor, none of bus request signals BSRQ0-BSRQ3 exists and when a flip-flop FF is reset, a bus-use permit signal BSAVc is sent out through only a NOR gate NOG3 immediately. Further, when plural bus request signals BSRQ0-BSRQ3 are inputted simultaneously and the bus request signal BSRQc is inputted from the processor during the processing, it is processed while given priority over the bus request signals BSRQ0-BSRQ3 enqueued when the flip-flop FF is reset on the completion of the transmission of the bus-use permit signal corresponding to the bus request signal being processed. |
