发明名称 ERASABLE PROGRAMMABLE READ ONLY MEMORY DEVICE
摘要 <p>PURPOSE:To increase the speed of reading operation by forming the device by a plurality of word lines, a digit line, a common source line and a resistance means. CONSTITUTION:A memory array MARY is constituted by a plurality of FAMOS transistors F1-F256, the word lines W1-W256 and the digit lines D1-Dn. The control gates of the FAMOS transistors F arranged in the same line are each connected in common with the corresponding word lines W1-W256, and the drains of the FAMOS transistors F arranged in the same row are each connected in common with the corresponding digit lines D1-Dn. the sources of the FAMOS transistors F constitute a common source line SL by being integrally formed by a common semiconductor region, and are divided. The source line is divided into the common source lines SL1-SL4 of the FAMOS transistors at every memory array MARY1-MARY4 relating to common digit lines CD1- CD4, and depletion type MOSFETs Q1-Q4 as the resistance means are each formed to each common source line SL1-SL4.</p>
申请公布号 JPS5987854(A) 申请公布日期 1984.05.21
申请号 JP19820197518 申请日期 1982.11.12
申请人 HITACHI SEISAKUSHO KK 发明人 FUKUDA MINORU;FURUSAWA KAZUNORI
分类号 H01L27/10;G11C16/06;G11C17/00;H01L21/8247;H01L29/788;H01L29/792 主分类号 H01L27/10
代理机构 代理人
主权项
地址
您可能感兴趣的专利