发明名称 |
Digital data processor with two operation units |
摘要 |
In a data processing apparatus executing a plurality of instructions in a pipeline mode by dividing each of the instructions into a plurality of stages, its operation circuit includes a first execution (E) unit capable of execution of operations required by all of the plural instructions and a second E unit capable of execution of operations required by part of the plural instructions only. A queue of data including decoded information of the instructions required for execution of operation stages are stored in a circuit to be selectively supplied by first and second circuits to the first and second E units, respectively. The first and second circuits sequentially select succeeding data in synchronism with the end of operations in the first and second E units respectively. As a result, when a stage of a succeeding instruction requires the result of operation of a preceding instruction being executed, that stage of the succeeding instruction is executed after the second E unit completes the operation of the preceding instruction, even when the first E unit is executing an instruction further preceding the preceding instruction.
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申请公布号 |
US4532589(A) |
申请公布日期 |
1985.07.30 |
申请号 |
US19820446002 |
申请日期 |
1982.12.01 |
申请人 |
HITACHI, LTD. |
发明人 |
SHINTANI, YOICHI;WADA, KENICHI;SHIMIZU, TSUGUO;YAMAOKA, AKIRA |
分类号 |
G06F9/38;(IPC1-7):G06F9/38;G06F9/00 |
主分类号 |
G06F9/38 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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