| 摘要 |
<p>In an integrated circuit a random access read/write memory array, said memory array with m pairs of bit lines, each pair of bit lines including a first bit line and a second bit line; n pairs of word-drain lines, each pair of word-drain lines including a word line and a drain line; each of said m columns of memory cells being connected between the first bit line and the second bit line of a discret one of said m pairs of bit lines; each of said n rows of memory cells being connected between the word line and drain line of a discrete one of said n pairs of word-drain lines; controllable read/write address decoder circuit means for reading the binary bit ("0" or"1") stored in any predetermined one of said m x n array of memory cells, or writing a binary bit ("0" or "1") in any predetermined one said m x n array of memory cells; and with n identical write enhancement circuit means for enhancing the operation of said random access read/write memory, each of said n identical write enhancement circuit means being a two-terminal device and each of said n identical circuit means being connected between the word line and the drain of a discrete one of said n pairs of word-drain lines. </p> |
