| 摘要 |
PURPOSE:To make it unnecessary to transfer a data between line buffers by applying a control signal from the outside to a line address control part of an information storage part, and determining a start line address and a final line address of read-out and write of an information storage part. CONSTITUTION:A line address control circuit 45 for inputting a control signal 101 outputs a line address signal 103 to RAMs 41, 42, etc., when a clock signal 102 is H, and writes a data on an input signal line 51 to the corresponding address of the signal 103 of the RAM 31, and the data on the line 51 to the corresponding address of the signal 103 of the RAM 42, when the signal 102 is L and also an output signal 104 of an input/output information control circuit 46, and when the data 104 is H, respectively. Also, when the signal 104 is L or H, a data on a signal line 52 or 53 of the RAM 41 or 42 is selected, respectively, outputted onto an output signal line 54, and when the signal 104 is L or H, the data on the line 53 or 52 is selected, respectively, and outputted onto an output signal line 55. |
