发明名称 PHASE LOCKED OSCILLATOR
摘要 PURPOSE:To hold an output frequency to a value before a fault takes place even if a reference input signal is faulty by providing a logic circuit blocking a clock signal to a counter circuit in response to an output signal of a fault detection circuit. CONSTITUTION:If a fault takes place in the reference input signal given to an input terminal 100, a fault detection circuit 7 detects the fault immediately and produces a logic level 0. As a result, a clock signal from a clock generating circuit 6 is blocked by a logic circuit 8 and not given to a counter circuit 3. Thus, an output signal of the counter circuit 3 keeps the value before a fault takes place in the reference input signal. Thus, the output voltage of the D/A converter circuit 4 converting the signal into an analog voltage, that is, the control voltage of the voltage-controlled oscillator 5 keeps the value before a fault takes place in the reference input signal, then the output frequency of the voltage controlled oscillator 5 remains unchanged, that is, a value before the fault takes place in the reference input signal.
申请公布号 JPS6373717(A) 申请公布日期 1988.04.04
申请号 JP19860216995 申请日期 1986.09.17
申请人 NEC CORP 发明人 MUTO HIROSHI
分类号 H03L7/14 主分类号 H03L7/14
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