| 摘要 |
A semiconductor memory device having a plurality of word line pairs and drain lines, a plurality of bit line pairs, and a plurality of memory cells connected to both of the word line pairs and the bit line pairs at the cross points thereof, comprising: a first and a second word line provided as the word line pair, a memory cell including a first and a second multi-emitter transistor whose commonly connected emitters are connected to the drain line, first and second resistors where one of their ends are connected between the collectors of the first and second multi-emitter transistors respectively, and where their other ends are both connected to the first word line and the bases of the second and first multi-emitter transistors are connected to the other's collectors, respectively, and first and second diodes such as Schottky barrier diodes are connected between the collectors of the first and second multi-emitter transistors and the second word line, respectively. A current which is provided for each row which consists of an input transistor which receives an address input signal at its base input and a reference transistor which receives a predetermined voltage at its base input with the emitters thereof being commonly connected with each other. Third and fourth resistors are serially connected between the collector of the input transistor and a power supply voltage. A first word line driving transistor for driving the first word line whose base is connected between the third resistor and the fourth resistor and whose emitter is connected to the first word line. A second word line driving transistor for driving the second word line whose base is connected between the collector of the input transistor and the fourth resistor and whose emitter is connected to the second word line. The collectors of the first and the second word line driving transistor are connected to the voltage power supply.
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