| 发明名称 |
High speed parity prediction for binary adders. |
| 摘要 |
<p>Parity for every byte of the sum produced by addition of two operands is predicted based upon segmentation of each sum byte into three groups of adjacent bits, which leads to Boolean minterm circuitry employing a minimum of exclusive-OR gates.</p> |
| 申请公布号 |
EP0339296(A2) |
申请公布日期 |
1989.11.02 |
| 申请号 |
EP19890105758 |
申请日期 |
1989.04.01 |
| 申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
VASSILIADIS, STAMATIS;SCHWARZ, ERIC MARK |
| 分类号 |
G06F7/00;G06F7/499;G06F11/10 |
主分类号 |
G06F7/00 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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