| 摘要 |
<p>A filter circuit uses a reversible counter (31) to eliminate noise from an input signal (5) which changes between high and low levels. The input signal (5) is sampled in response to a clock signal (7) of selected frequency and the reversible counter is incremented by a sampled value at the high level and decremented by a sampled value at a low level. A hysteresis is built into the counting sequence by jumping the count by a predetermined value when the count is incremented over a first threshold value or decremented below a second threshold value.</p> |
