| 摘要 |
Time sharing log input signals and weight data, which are inputted sequentially via analog signal buses, are subjected to sum/product operation. An analog neuron processor (ANP) outputs a signal to the analog signal buses through a non-linear circuit. The neutral network is controlled by reading required data from a control- pattern memory and required weight data from a weight memory under the control of a microsequencer, to obtain a practically operable neurocomputer. In this neurocomputer, a number of ANPs are connected by one analog bus. This enables the number of wires in the neutral network to be reduced greatly and the scale of the circuit to be minimised. |
