| 摘要 |
<p>This invention discloses a dynamic type random-access memory which includes a bit line pair, a memory cell array including a plurality of memory cells (MCi; i = 0 to 255), a bit line sense amplifier (NA, PA) which is enabled after data written in one of the plurality of memory cells (MCi; i = 0 to 255) is read out onto the bit line pair, and a charge transfer circuit (NT1, NT2) which is connected between the bit line pair and sense nodes (SN, SN) of the bit line sense amplifier (NA, PA), and is kept OFF for a predetermined period of time after a sense amplification operation of the bit line sense amplifier (NA, PA) is started.</p> |
