| 摘要 |
The logic operatior processing unit processes, in two demension user program programmed using ladder diagram by block units. The unit includes a result processing unit (RPU) for processing the operated result of a CPU, a sequential control unit (SU) for generating control clock signal and enable signal according tothe output signal of the result processing unit, a timing decode unit (TDU) for decoding address signals transmitted from a CPU to generate timing clock signal, a control unit (CU) for generating control signals by the output signal of the SU and address signals of a CPU, a buffer (BUF2) for buffering address signals generated by a CPU, and address memories (AM0-AM7) for storing address signals generated by a CPU.
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