| 摘要 |
PROBLEM TO BE SOLVED: To provide a processor architecture by which operations requiring handling upon exiting a low power state are handled in a power sensitive manner.SOLUTION: The present invention provides a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core in response to the interrupt, and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination result is affirmative, but otherwise providing the large core execution state and the resume signal to the large core.SELECTED DRAWING: Figure 4 |
