Duty cycle detection and correction circuit in an integrated circuit

摘要

A clock generating circuit includes a clock generator, a first clock tree, a second clock tree, and a duty cycle correction circuit. The clock generator is configured to generate a first clock signal and a second clock signal. The first clock tree includes a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals. The second clock tree includes a driver cell configured to generate a third output clock signal based on the set of control signals. The duty cycle correction circuit is configured to receive the first output clock signal and the second output clock signal and to generate the set of control signal based on the first output clock signal and the second output clock signal.

主权项

1. A clock generating circuit, the circuit comprising:
a clock generator configured to generate a first clock signal and a second clock signal, the first clock signal and the second clock signal having a predetermined phase difference; a first clock tree comprising a driver cell configured to generate a first output clock signal based on the first clock signal and a set of control signals, and to generate a second output clock signal based on the second clock signal and the set of control signals; a second clock tree comprising a driver cell configured to generate a third output clock signal based on the first clock signal and the set of control signals; and a duty cycle correction circuit configured to receive the first output clock signal and the second output clock signal and to generate the set of control signals based on the first output clock signal and the second output clock signal.