| 摘要 |
<p>An I/O controller (10) for transferring data between a host processor (12) and one or more I/O units (15-18). The controller interleaves processor command transfers (PIO) in the midst of direct memory access (DMA) transfers without repeated data moves. DMA transfers are suspended temporarily during the priority PIO transfer. An interrupt Scanner, for scanning the various I/O units, is also prioritized with respect to DMA and PIO transfers. <IMAGE></p> |
