| 摘要 |
The generated comprises the following means; on inverter (I1) which outputs the inverted bi-phase signal (BPD) coming from transmission line (30); a first edge signal detector (10) outputting the falling edge of the BPD signal; an OR gate (O1) outputting the logic add signal of the first and second edge signal detectors; a nand gate (NA1) outputting the inverted logic multiplication of the two inputs, one from the OR gate output and the other from a clock signal of a period.
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