Register with selective wait feature

摘要

A register having a selective wait feature includes logic for receiving a new value to be stored and logic for selectively delaying the appearance of the new value at the output of the register until some predetermined event has occurred. The register can also be read to determine whether the event has occurred. The register is disclosed in the context of a microprocessor-controlled digital timer apparatus which responds to an incoming pulse train. Certain control bits in the apparatus determine whether the digital timer is responsive to rising edges of the pulse train, falling edges, any edges, or no edges. The microprocessor determines, at the time new values are stored to those control bit locations, whether the new values are to become effective immediately or are to be delayed until some intervening event has occurred. The register permits control over the time at which transitions between different operating modes are made in order to assure orderly operation.