| 摘要 |
The invention includes a data memory having sequentially stored N-bit words that are each a binary description of a time at which an event is to occur. Also stored is a K-bit word, associated with each N-bit word, that is a binary description of what the scheduled event is to be. The invention utilizes a free-running clock and clock circuitry to gauge when an event should occur. The clock circuitry tallies an N-bit description of running time. M-bits of the N-bit description of running time are specified by a single fast synchronous counter. The remaining N-M bits are specified by two slow counters each of N-M bit capacity. Because incrementation of slow counters creates count settling times that may significantly affect accurate event sequencing, the slow counters are alternately incremented and a multiplexer is used to switch to the counter that will provide a "steady state" count at a scheduled event time. A comparator is used to judge when the stored N-M bit description of time equates with the N-M bits counted in the utilized slow-speed counter. An equality then enables an M-bit comparison with the stored M-bit portion of the description of a scheduled event time. When the stored and elapsed M-bits equal, the stored K-bit word describing the scheduled event is made valid so that the event occurs at the selected time.
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