BIP TYPE DATA OPERATER

摘要

The bit interleaved parity (BIP) performance data processor comprises a BIP error counting circuit for generating a 4-bit BIP error count, a performance data accumulating circuit for storing the 4-bit BIP error count by a low-speed frame period, and a microprocessor interface circuit for reading performance data by the control of a microprocessor and clearing the performance data, thereby simplifying a circuit construction.