发明名称 |
Digital modulator and demodulator circuit |
摘要 |
In a digital modulator circuit for modulating a fixed-length code into a variable-length code and a digital demodulator for demodulating a variable-length code into a fixed-length code in a parallel data form, pre-modulation and pre-demodulation data is input to a logic circuit in synchronization with a pulse input, while a remainder of the fixed-length or variable-length code digital parallel input data taking place in modulating or demodulating process is fed back as an input to the logic circuit via a flip-flop to modulate or demodulate the data together with pre-modulation or pre-demodulation parallel data input at the next input pulse in a parallel data form. A post-modulation or post-demodulation data as well as a modulation or demodulation bit number output from the logic circuit are input to the buffer circuit to output post-modulation or post-demodulation data of which bits have been all modulated or demodulated.
|
申请公布号 |
US5422641(A) |
申请公布日期 |
1995.06.06 |
申请号 |
US19920986966 |
申请日期 |
1992.12.08 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
KOBAYASHI, YOSHIHARU |
分类号 |
H03M5/14;(IPC1-7):H03M7/40 |
主分类号 |
H03M5/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|