Multi-gate data storage arrangement for computer

摘要

The multi-gate data storage arrangement has a write-read-memory element and data registers and time multiplexers to coordinate data transfer between the gates and the memory element. The memory element is space multiplex and has m*n bit data in/outputs in the data transfer connection plane (DAE). The gates each have a word width of n-bits and are connected to the data registers (DER, DAR, SR) and the memory element so that the nth plane of the gates is connected via time multiplex element (AMUX1, AMUX2, EMUX, BSMUX) one above the other and with the respective n-plane of the memory element to the width of m words.