发明名称 |
A DIGITALLY CONTROLLED FIRST ORDER JITTER ATTENUATOR USING A DIGITAL FREQUENCY SYNTHESIZER |
摘要 |
A circuit for attenuating phase jitter on an incoming clock signal includes a digital frequency synthesizer, and a phase lock loop including a phase detector. The digital phase detector compares the phase relationship between an incoming signal and a clock signal generated by the digitally controlled frequency synthesizer and produces an output signal proportional to the phase difference. The output signal comprises both a direction indicator and a magnitude indicator for controlling the digitally controlled frequency synthesizer. One of a plurality of phases of a voltage controlled oscillator (VCO) are selected in response to the output signal to alter the frequency of the clock signal.
|
申请公布号 |
WO9519067(A1) |
申请公布日期 |
1995.07.13 |
申请号 |
WO1994US14892 |
申请日期 |
1994.12.30 |
申请人 |
LEVEL ONE COMMUNICATIONS, INC. |
发明人 |
GOSHAL, SAJOL, C. |
分类号 |
H03L7/081;H03L7/085;H03L7/099;(IPC1-7):H03L7/081 |
主分类号 |
H03L7/081 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|