| 摘要 |
A non-volatile memory cell (2) including a floating gate (16) dielectrically disposed between a first control gate (12) and a second control gate (14). Addressing of the memory cell (2) for programming, de-programming and reading involves the simultaneous energization of both the control gates (12 and 14). The energization of only one control gate, but not both, can not activate the memory cell (2). A memory cell array comprising the memory cells of the present invention can be arranged in a matrix format. Addressing of each of the memory cell (2) in the array is simply the simultaneous energization of a pair of control gates (12 and 14) perpendicularly criss-crossing the underlying memory cell. Further modifications in the design of the memory cell (2) enable the memory cell to be programmed with negative threshold voltages, thereby relaxing the manufacturing tolerances, and consequently reduces the production cost. |
