Matrix circuit multiplier for binary coded numbers

摘要

The multiplier uses BOOTH circuitry with carry-save logic and has a number of multiplexer rows (R1,R2,R4,R6) followed by summing rows (R3,R5,R7) in which the sign bits of partial products (a8,a7,a6...) are added. The output of the highest value BOOTH multiplexer (M18) in the first multiplexer row provides an inverted sign bit (a8) as input for a cascaded adder (VA) in the next summation row. This adder also receives a constant logic one input and a partial product bit input (b6). The adders in the following summing rows are similarly supplied with the outputs of the Booth multiplexer in the preceding multiplexer row, and the outputs of the final summation row (R7) are connected to a final adder (FA).