| 摘要 |
A data processing system (10) having address pins (30), data pins (31), control pins (32), chip select pins (33), and other pins (34). For bus cycles of an instruction which do not require use of an external address bus (35), the values driven by the address pins (30) are "frozen" in their previous logic state. The previous logic state is determined by the most recent value driven by address pins (30) during a bus cycle that required use of the external address bus (35). Data pins (31) may be "frozen" in the same manner as address pins (30). Control pins 32, chip select pins 33, and other pins 34 may be driven to their respective inactive logic states. The goal is to reduce noise and power consumption by reducing the voltage level switching taking place on external conductors (35-39).
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