| 摘要 |
The variable length decoder which separates the code word from the inputted bit stream by rearranging a code word table recommended by CCITT and can decode the code word by variable length decoding(VLD) and comprises: a memory(22) which stores a table for VLD corresponding to the code word to use the code word as address; a low address generating part which generates the low address of a memory(22), and comprises a "1" detecting and maintaining part(16), an AND gate(18) and a shifter(20); a high address generating part(24) which generates the high address of the memory(22) by bit "0" prior to the first bit "1" of the code word; a clock masking signal generating part(26) which controls the high address generation before the first bit "1" of each code word is detected and controls the low address generation after the first bit "1" of each code word is detected, and comprises a counter(10), a latch(12) and a clock masking(14).
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