Method and arrangement for clock adjustment using programmable period binary rate multiplier

摘要

A method and arrangement for adjusting a clock frequency to allow computer devices with different clock frequencies to operate together. The arrangement scales the input clock frequency to be scaled by any desired fraction by controlling both the numerator and denominator of the scaling fraction. Clock frequency adjustment is achieved by transforming the input clock frequency into a periodic clock frequency that is reset following a desired clock period and scaling this periodic clock frequency according to a desired divisor value to generate the desired clock frequency.