Single core wakeup multi-core synchronization mechanism

摘要

A microprocessor includes a plurality of cores, a shared cache memory, and a control unit that individually puts each core to sleep by stopping its clock signal. Each core executes a sleep instruction and responsively makes a respective request of the control unit to put the core to sleep, which the control unit responsively does, and detects when all the cores have made the respective request and responsively wakes up only the last requesting cores. The last core writes back and invalidates the shared cache memory and indicates it has been invalidated and makes a request to the control unit to put the last core back to sleep. The control unit puts the last core back to sleep and continuously keeps the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory was invalidated, and is put back to sleep.

主权项

1. A microprocessor, comprising:
a plurality of cores; a cache memory shared by the cores; and a control unit, configured to individually put each of the cores to sleep by stopping a clock signal to the core; wherein each of the cores is configured to execute a sleep instruction and in response to make a respective request of the control unit to put the core to sleep; wherein the control unit is configured to:
put each of the cores to sleep in response to the respective request; anddetect when all of the cores have made the respective request to be put to sleep and in response to wakeup only a last of the cores to make the respective request; wherein the last of the cores is configured to:
write back and invalidate the shared cache memory and indicate that the shared cache memory has been invalidated; andmake a request to the control unit to put the last core back to sleep; wherein the control unit is configured to:
put the last core back to sleep and continuously keep the other cores asleep while the last core writes back and invalidates the shared cache memory, indicates the shared cache memory has been invalidated, and is put back to sleep.