The circuit has a clock input driver (11) arranged in a main plane of a semiconductor substrate. An input node of the input driver is electrically connected to a pad (12) via an input line (13). The circuit also has several front drivers (15) arranged spaced apart. Input nodes of the front drivers are electrically connected to a common line (16). The line is electrically connected to an output node of the input driver. Output nodes of the front drivers are electrically connected to a second common line (18). Several main drivers (19) are arranged at fixed spacing on the main plane of the substrate. Input nodes of the main drivers are electrically connected to the second line. Output nodes are electrically connected to a third common line (22). The latter is connected to a number of clock signal supply lines (21). These are electrically connected to clock input nodes of several internal circuits (20) which each require a clock signal.
