Dual phase-locked loop clock synthesizer

摘要

A dual phase-locked loop (PLL) clock synthesizer is disclosed for generating clock signal in synchronization with the data input signal received over a network environment. The dual PLL clock synthesizer is suitable for processing data streams of any bit sequence without data error caused by interference due to clock signal jittering phenomena. The dual PLL clock synthesizer is particularly suitable for application to high-speed Ethernet network environment such as for decoding to obtain the original data conveyed over the network through selected encoding scheme.