| 摘要 |
A processing unit (100) with a processor (110) for processing an operation code and a method for processing the operation code in the processing unit (100). The processor (110) comprises an operation code control unit (200) for receiving and processing the operation code in a boolean circuit (230) and generating a logical result thereof, and a next address control unit (210) comprising a multiplexing unit (250) with a plurality of input lines (A-D) selectable by the multiplexing unit (250) by means of the logical result of the boolean circuit (230). The processor (110) is triggerable by a trigger signal (CLOCK) and each operation code is processable by the processor (110) between successive trigger signals (CLOCK). When the trigger signal appears, the processor (110) issues a signal comprising an address of the operation code to be processed to the control memory (129) and/or a user data memory (140). The operation code corresponding to that address is loaded from the control memory (120) to the processor (110) and processed therein. One result of this processing is that the address of the successive operation code, which will be processed when the successive trigger signal appears. This loading and processing of operation code happens continuously in each cycle between successive trigger signals, until the end of program is reached or an interrupt signal is calling a stop routine. Each operation code is processed between successive trigger signals (or within one CLOCK cycle) allowing a predictable timing of a sequence of operation codes so that a real time condition is achievable.
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