发明名称 INTEGRATED CIRCUIT, MANUFACTURING METHOD THEREOF AND METHOD OF EVALUATING INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method of manufacturing an integrated circuit easy to evaluate its bond condition. SOLUTION: Two external connecting electrodes 12 are provided on the surface of a chip 11, via-holes 13 are formed in their lower parts, and conductors 14 are formed in the via-holes 13. On the back surface of the chip 11 a first metal film 15 is formed, a second metal film 19 is formed on the surface of a ceramic substrate 18, and both are contacted and heated to bond the chip 11 to the substrate 18. Before forming the first film, slits 16 have been provided without the first metal film. At evaluating the bonding condition, the resistance between the two external connecting electrodes 12 is measured.
申请公布号 JPH10125741(A) 申请公布日期 1998.05.15
申请号 JP19960273512 申请日期 1996.10.16
申请人 OKI ELECTRIC IND CO LTD 发明人 IKETANI MASAHISA;INOGUCHI KAZUYUKI
分类号 G01R31/26;H01L21/60;H01L21/66;H01L23/48;H01L23/544;(IPC1-7):H01L21/60 主分类号 G01R31/26
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