发明名称 Data processing apparatus having a clock control unit for decreasing power consumption of a central processing unit
摘要 In a CPU comprising a CPU section and a BCU section, the processing speed of the CPU section is prevented from decreasing, the amount of power consumed by the CPU section is reduced, and the need of a wait control function in the CPU section is eliminated. A clock control section 105c distributes an externally supplied clock 111 to the inside of a CPU section 101 and a BCU section 105. During a read access request from the CPU section 101 to a storage device 106, the period of a CPU clock 112 supplied to the CPU section 101 is extended. That is, the state immediately before the change point of the CPU clock 112 when the CPU section 101 inputs input data via an internal data bus 104 is extended until read data has been established on the internal data bus 104.
申请公布号 US5850541(A) 申请公布日期 1998.12.15
申请号 US19970790805 申请日期 1997.01.30
申请人 NEC CORPORATION 发明人 SUGIMOTO, HIDEKI
分类号 G06F9/30;G06F1/04;G06F1/32;G06F13/42;(IPC1-7):G06F1/04 主分类号 G06F9/30
代理机构 代理人
主权项
地址