| 发明名称 |
Multi-channel parallel to serial and serial to parallel conversion using a RAM array |
| 摘要 |
A circuit to implement a multi-channel parallel to serial conversion and a multi-channel serial to parallel conversion in one minimal RAM Matrix. The number of RAM cells (bits) needed is equivalent to the number of Flip-Flops used in a standard shift register and holding register implementation.
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| 申请公布号 |
US5926120(A) |
申请公布日期 |
1999.07.20 |
| 申请号 |
US19960624856 |
申请日期 |
1996.03.28 |
| 申请人 |
NATIONAL SEMICONDUCTOR CORPORATION |
发明人 |
SWENSON, ERIK RUSTAN;EDEM, BRIAN CHARLES |
| 分类号 |
H03M9/00;(IPC1-7):H03M9/00 |
主分类号 |
H03M9/00 |
| 代理机构 |
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