发明名称 |
Programmable logic device incorporating a memory efficient interconnection device |
摘要 |
The invention relates to an integrated circuit that incorporates a memory efficient interconnection device. Typically, the integrated circuit chip is a complex programmable logic device architecture (CPLD). By using the memory efficient interconnection device, the invention is able to reduce the quantity of memory resources required to program the interconnection device while at the same time not substantially sacrificing the probability of fitting logic functions in the CPLD. The reduction in memory resources that the CPLD must provide leads to increased availability of precious die area for other components of the CPLD.
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申请公布号 |
US6057707(A) |
申请公布日期 |
2000.05.02 |
申请号 |
US19980016209 |
申请日期 |
1998.01.30 |
申请人 |
ALTERA CORPORATION |
发明人 |
SCHLEICHER, JAMES;FERRAZANO, MICHAEL J. |
分类号 |
H03K19/177;(IPC1-7):H03K19/177;H03K19/173;H03K19/094 |
主分类号 |
H03K19/177 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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