| 摘要 |
PROBLEM TO BE SOLVED: To reduce power consumed by a cache circuit, to accelerate the speed of data retrieval and to accelerate a processing speed by retrieving data from an output buffer in the case that the data relating to a memory address are stored in the output buffer. SOLUTION: The output of a cache memory is latched to the output buffer. At the time of receiving the memory address, a cache judges whether or not the data relating to the memory address are stored in the output buffer, and in the case that they are stored there, the data are retrieved from the output buffer. In the case that they are not stored there, the cache judges whether or not the data relating to the memory address are stored in the cache memory. For instance, this cache architecture 50, a cache controller 52 receives the memory address. The cache controller 52 is provided with an internal register and it stores the address of a usable data column in the output buffer of a data array 56.
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