| 摘要 |
PROBLEM TO BE SOLVED: To provide a DRAM(dynamic random-access memory) control circuit in which circuit constitution is simplified, operation speed is increased, and circuit scale is small. SOLUTION: A RAS(row address select) generating circuit 104 generates a RAS signal based on a CPU-ASTB (address strobe) signal and a CLKOUT signal outputted by a CPU 101. An address decoding circuit 103 generates a/CS- DRAM signal based on ADD 0-19 signals. A CAS generating circuit 106 generates a/CAS(column address select) signal and an ADD-SEL signal based on a/RAS2 signal, a/CS-DRAM signal, and a CPU-ASTB signal. An address switching circuit 102 outputs ADD 0-9 or ADD 10-19 as RAM-ADD 0-9 signals based on a value of the ADD-SEL signal.
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