发明名称 Processor having selective branch prediction
摘要 A data system capable of selecting whether to utilize address prediction based on the state of an address prediction enable signal. When employing address prediction, the outcome of branch instructions are presumed prior to the resolution of the instruction. When not using address prediction, the system waits until a branch instruction is resolved before fetching the next address to be executed. At least one embodiment of a method and data system disclosed herein makes use of the different setup timing available when employing prediction and non-prediction modes of operation.
申请公布号 AU6302601(A) 申请公布日期 2001.12.24
申请号 AU20010063026 申请日期 2001.05.10
申请人 MOTOROLA, INC. 发明人 WILLIAM C. MOYER;JEFFREY W. SCOTT
分类号 G06F9/32;G06F9/38 主分类号 G06F9/32
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