| 摘要 |
A distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The address switch connects to each of the node controllers and to each of the memory subsystems, and each of the memory subsystems connects to the address switch and to each of the node controllers. The node controller receives commands from a master device. The buses between the master devices, the node controllers, the address switch, and the memory subsystems are operable using a variety of bus protocols. A response combination block connects to the address switch, to each master device, to each node controller, and to each memory subsystem in order to receive, logically combine/generate, and then transmit command status signals and command response signals associated with commands issued by master devices. The response combination block generates signals based on whether a master device port is in a local cycle during which a master device may issue a command on the master device port and based on whether the data processing system is in a global cycle during which the address switch broadcasts or snoops a command.
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