Multi-Package Segmented Data Transfer Protocol for Solid-State Drive Applications

摘要

A memory controller receives a command to perform a memory operation, the command including a data packet comprising a plurality of data divisions. In response to receiving the command, for each individual memory device, the memory controller assigns to the individual memory device a respective data division, the respective data division including a plurality of data segments, and determines a single relative memory address associated with an address specified by the received command. The memory controller assembles a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous instruction portion, and transmits the sub-request to every memory portion of the number of memory portions of the individual memory device.

主权项

1. A method of performing memory operations in a storage system, the storage system having one or more memory controllers and a set of memory devices, each memory device comprising a number, greater than one, of memory portions, the method comprising:
at a memory controller: in response to receiving a host command to perform a memory operation, wherein the host command includes a data packet comprising a plurality of data divisions, for each individual memory device of a plurality of memory devices in the set of memory devices:
assigning to the individual memory device a respective data division of the plurality of data divisions, wherein the respective data division includes a plurality of data segments, and each of the data segments of the respective data division corresponds solely to a distinct individual one of the memory portions of the individual memory device;determining a single relative memory address associated with an address specified by the received host command;assembling a sub-request comprising a single contiguous instruction portion, which includes the single relative memory address and one or more instructions to perform the memory operation, and the respective data division, the respective data division following the single contiguous address portion; andtransmitting the sub-request to every memory portion of the number of memory portions of the individual memory device.