| 摘要 |
For controlling the sampling timing of a digital data receiver (2) with the aid of a timing control loop (3-6), it is proposed that the timing control criterion (Trk) for the timing control loop is obtained by combining a first portion (Trk1) with a second portion (Trk2). The first portion (Trk1) of the timing control criterion is obtained by evaluating the input and output signals of the decision element (8) of the digital receiver (2), while the second portion (Trk) is obtained by evaluating at least one coefficient (C-1) of the adaptive equaliser (7) of the digital receiver (2). In this way, favourable jitter characteristics and also a stable control response are achieved.
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