PILLAR ARRANGEMENT IN NAND MEMORY

摘要

Embodiments of the present disclosure are directed towards techniques and configurations for providing a 3D memory array apparatus. In one embodiment, the apparatus may comprise a substantially hexagonal arrangement having seven pillars disposed in a die in a repeating pattern. The arrangement may include first and second pillars disposed at a pillar pitch from each other in a first row; third, fourth, and fifth pillars disposed at the pillar pitch from each other in a second row; and sixth and seventh pillar disposed at the pillar pitch from each other in a third row and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a direction that is substantially orthogonal to bitlines disposed in the die. Each pillar in the arrangement may be electrically coupled with a different bitline. Other embodiments may be described and/or claimed.

主权项

1. A method, comprising:
disposing a plurality of bitlines in a die; disposing a substantially hexagonal arrangement having seven pillars in the die, including:
disposing first and second pillars at a pillar pitch from each other in a first row of the arrangement;disposing third, fourth, and fifth pillars at the pillar pitch from each other in a second row of the arrangement;disposing sixth and seventh pillars at the pillar pitch from each other in a third row of the arrangement and shifted relative to the first and second pillars respectively by a quarter of the pillar pitch in a first direction that is substantially orthogonal to the plurality of bitlines disposed in the die, and shifted relative to the third and fourth pillars by the quarter of the pillar pitch in a second direction that is substantially orthogonal to a plurality of bitlines, wherein each pillar in the arrangement is electrically coupled with a different bitline of the plurality of bitlines, wherein the second row is located between the first and third rows; andelectrically coupling each of the pillars in the arrangement with a drain-side select gate (SGD); and electrically coupling each pillar in the arrangement with a different bitline of the plurality of bitlines.