| 发明名称 |
Aspect ratio trapping and lattice engineering for III/V semiconductors |
| 摘要 |
A semiconductor structure including a III/V layer on a SiGe layer, edges of the SiGe layer are relaxed, the III/V layer is a semiconductor in a III/V semiconductor group, the SiGe layer is directly on an insulator layer, barrier layers on two adjacent sides of the SiGe layer and the III/V layer, and the barrier layer is directly on the insulator layer. |
| 申请公布号 |
US9627491(B2) |
申请公布日期 |
2017.04.18 |
| 申请号 |
US201615098683 |
申请日期 |
2016.04.14 |
| 申请人 |
International Business Machines Corporation |
发明人 |
Cheng Kangguo;Hashemi Pouya;Khakifirooz Ali;Reznicek Alexander |
| 分类号 |
H01L29/267;H01L21/02;H01L21/762;H01L21/18;H01L29/06;H01L29/32 |
主分类号 |
H01L29/267 |
| 代理机构 |
|
代理人 |
Kelly L. Jeffrey |
| 主权项 |
1. A structure comprising:
a III/V layer on a SiGe layer, edges of the SiGe layer are relaxed, the III/V layer is a semiconductor in a III/V semiconductor group, the SiGe layer is directly on an insulator layer; and barrier layers on two adjacent sides of the SiGe layer and the III/V layer, the barrier layer is directly on the insulator layer. |
| 地址 |
Armonk NY US |
